DEVELOPMENT OF AN IMPROVED FRAME LEVEL REDUNDANCY SCRUBBING ALGORITHM FOR STATIC RANDOM ACCESS MEMORY BASED FIELD PROGRAMMABLE GATE ARRAY

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dc.contributor.authorHARUNA, Ocholi Enoch
dc.date.accessioned2018-08-14T10:59:53Z
dc.date.available2018-08-14T10:59:53Z
dc.date.issued2017-07
dc.descriptionA THESIS SUBMITTED TO THE SCHOOL OF POSTGRADUATE STUDIES, AHMADU BELLO UNIVERSITY, ZARIA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE AWARD OF MASTER OF SCIENCE (M.Sc) DEGREE IN ELECTRONICS ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING FACULTY OF ENGINEERING AHMADU BELLO UNIVERSITY, ZARIA NIGERIAen_US
dc.description.abstractThe use of Static Random Access Memory (SRAM)-based Field Programmable Gate Array (FPGA) in critical applications has been considered a solution in space and avionics domain due to its flexibility in achieving multiple requirements such as re-programmability and good performance. However, SRAM-based FPGAs are susceptible to radiation induced Single Event Upset (SEU) that affects the functionality of the implemented design. This research presents the development of an improved Frame Level Redundancy (FLR) Scrubbing algorithm for SRAM-based FPGA to mitigate against radiation-induced SEU. The improved FLR uses Cyclic Redundancy Check (CRC) as an error detection technique to enable configuration memory scrubbing as a solution to mitigate SEU through upset detection and correction. Fault injection was performed on FPGA configuration memory frames on different number of modules to emulate SEU. The improved FLR algorithm was implemented and system level simulation was carried out using MATLAB R2013a. The performance of the improved FLR algorithm was compared with that of the existing FLR algorithm using error correction time and energy consumption as metrics. The results of this work showed that the improved FLR algorithm produced 31.6% improvement in error correction time and 61.1% improvement in energy consumption over the existing FLR algorithm.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/10100
dc.language.isoenen_US
dc.subjectDEVELOPMENT,en_US
dc.subjectIMPROVED FRAME,en_US
dc.subjectLEVEL REDUNDANCY,en_US
dc.subjectSTATIC RANDOM ACCESS MEMORY,en_US
dc.subjectFIELD PROGRAMMABLE GATE ARRAY,en_US
dc.subjectSCRUBBING ALGORITHM,
dc.titleDEVELOPMENT OF AN IMPROVED FRAME LEVEL REDUNDANCY SCRUBBING ALGORITHM FOR STATIC RANDOM ACCESS MEMORY BASED FIELD PROGRAMMABLE GATE ARRAYen_US
dc.typeThesisen_US
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